Title: Physical Design Engineer

Company: Intel Corporation

Location: San Jose, Calif.

Celebrating more than 40 years of experience in physical design, Billie Rivera continues to make strides in the Internet protocol arena through her position as physics design engineer at Intel Corporation. As a company dedicated to accessible technological innovation, Intel relies on Ms. Rivera’s abilities in physical design verification and management to further its corporate vision. In addition to physical verification, she dexterously completes tasks involving Megatest software flow, information technology debugging, and standard cell design kits. Her persistent work ethic and extensive background in the field leave no doubt as to her considerable value in this ever-expanding industry.

In 1970, Ms. Rivera got her start in technology working on an assembly line to make calculators for Hewlett-Packard. She steadily moved up in the field, and her more recent background includes time as worldwide manager of physical design and layout for Arasan Chip Systems, Inc. Employing a unique approach, she was notable for utilizing the inter-dependency of each development area in order to improve the knowledge and productivity of each of her team members. Through other experience with such companies as ARM Ltd. and Virtual Silicon, she has honed and exercised considerable skill in product verification, design implementation, and IP chip development. Ms. Rivera is also certified in a number of technology-relevant specialty areas including Synopyse Power Systems and Cadance Encounter SOC courses. She is currently studying at the University of California, Berkeley.

Committed to excellence in her field, Ms. Rivera maintains a membership with Analog Mixed Signal Layout Designers, COMPASS Alumni, Design Verification Group, IC Layout Designers, Mask Design Layout Engineers, and other prominent IT organizations. She has a number of inventions patented, including a method and apparatus for integrated circuit design with a software tool and an integrated circuit having a reduced spacing between a bus and adjacent circuitry. Passionate about new technologies and methodologies, it is Ms. Rivera’s personal goal to support technological progress and growth.